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In computer engineering, the creation and development of the pipeline burst cache memory is an integral part in the development of the superscalar architecture. It was introduced in the mid 1990s as a replacement for the Synchronous Burst Cache and the Asynchronous Cache and is still in use till date in computers. It basically increases the speed of the operation of the cache memory by minimizing the wait states and hence the processor computing speed. Implementing the techniques of pipelining and bursting, high performance computing is assured. It works on the principle of parallelism, the very principle on which the development of superscalar architecture rests. Pipeline burst cache can be found in DRAM controllers and chipset designs. == Introduction == In a processor-based system, the speed of the processor is always more than that of the main memory. As a result, unnecessary wait-states are developed when instructions or data are being fetched from the main memory. This causes a hampering of the performance of the system. A cache memory is basically developed to increase the efficiency of the system and to maximise the utilisation of the entire computational speed of the processor. The performance of the processor is highly influenced by the methods employed to transfer data and instructions to and from the processor.The less the time needed for the transfers the better the processor performance. The Pipeline Burst Cache is basically a storage area for a processor that is designed to be read from or written to in a pipelined succession of four data transfers. As the name suggests 'pipelining', the transfers after the first transfer happen before the first transfer has arrived at the processor. It was developed as an alternative to asynchronous cache and synchronous burst cache. It was first implemented in the year 1996 by Intel in the Pentium microprocessor. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Pipeline burst cache」の詳細全文を読む スポンサード リンク
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